1. Field of the Invention
The invention relates generally to semiconductor memory devices and, more particularly, to a method of manufacturing a flash memory device, in which an interference phenomenon between neighboring cells in high-integrated semiconductor devices can be minimized and the coupling ratio can be enhanced by controlling the effective field height (EFH) by etching an isolation film at a predetermined thickness.
2. Discussion of Related Art
A NAND flash memory device performs data program by injecting electrons into the floating gate by Fowler-Nordheim (FN) tunneling phenomenon, thereby proving a large capacity and a high degree of integration.
The NAND flash memory device includes a plurality of cell blocks. One cell block includes a plurality of cell strings in which a plurality of cells for storing data are in series connected to form one string, and a drain select transistor and a source select transistor formed between the cell string and the drain, and the cell string and the source, respectively.
The cell of the NAND flash memory device is formed by forming an isolation film on a semiconductor substrate, forming a gate in which a tunnel oxide film, a floating gate, a dielectric layer, and a control gate are stacked on the semiconductor substrate, and forming junction units on both sides of the gate. The isolation film and the floating gate are formed by a shallow trench isolation (STI), self-aligned shallow trench isolation (SA-STI), or self aligned floating gate (SAFG) process.
As the size of the NAND flash memory device decreases, however, the distance between the cells reduces and the operations of neighboring cells are influenced accordingly. As a result, the interference phenomenon between the neighboring cells whose states are changed becomes the most important problem. For example, upon programming, a threshold voltage of a program cell rises under the influence of the threshold voltages of neighboring cells due to the interference phenomenon between the neighboring cells. Accordingly, the distributions of the threshold voltage of the program cell are widely changed, resulting in failure of a chip. The interference problem between neighboring cells becomes more profound in multi-level cells. To minimize the interference phenomenon between the cells, the distance between the cells must be secured sufficiently. However, as the level of integration of devices is increased, to secure a sufficient distance between the cells has a limit.
Meanwhile, in the SA-STI process that is most widely used, a floating gate must be formed using first and second conductive layers and the second conductive layer must be patterned using the floating gate mask. However, as the level of integration of semiconductor devices is increased and the cell size decreases, the alignment margin is reduced. As a result, the process employing the floating gate mask is no longer used. 